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cy14c101j cy14b101j cy14e101j 1-mbit (128 k 8) serial (i 2 c) nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-54050 rev. *n revised november 7, 2013 1-mbit (128 k 8) serial (i 2 c) nvsram features 1-mbit nonvolatile static random access memory (nvsram) ? internally organized as 128 k 8 ? store to quantumtrap nonvolatile elements initiated automatically on power-down (a utostore) or by using i 2 c command (software store) or hsb pin (hardware store) ? recall to sram initiated on power-up (power-up recall) or by i 2 c command (software recall) ? automatic store on power-down with a small capacitor (except for cy14x101j1) high reliability ? infinite read, write, and recall cycles ? 1 million store cycles to quantumtrap ? data retention: 20 years at 85 c high speed i 2 c interface [1] ? industry standard 100 khz and 400 khz speed ? fast-mode plus: 1 mhz speed ? high speed: 3.4 mhz ? zero cycle delay reads and writes write protection ? hardware protection using write protect (wp) pin ? software block protection for 1/4, 1/2, or entire array i 2 c access to special functions ? nonvolatile store/recall ? 8 byte serial number ? manufacturer id and product id ? sleep mode low power consumption ? average active current of 1 ma at 3.4 mhz operation ? average standby mode current of 150 a ? sleep mode current of 8 a industry standard configurations ? operating voltages: ? cy14c101j: v cc = 2.4 v to 2.6 v ? cy14b101j: v cc = 2.7 v to 3.6 v ? cy14e101j: v cc = 4.5 v to 5.5 v ? industrial temperature ? 8- and 16-pin small outline in tegrated circuit (soic) package ? restriction of hazardous s ubstances (rohs) compliant overview the cypress cy14c101j/cy14b101j/cy14e101j combines a 1-mbit nvsram [2] with a nonvolatile element in each memory cell. the memory is organized as 128 k words of 8 bits each. the embedded nonvolatile elements incorporate the quantumtrap technology, creating the world?s most reliable nonvolatile memory. the sram provides infi nite read and write cycles, while the quantumtrap cells provide highly reliable nonvolatile storage of data. data transfer s from sram to the nonvolatile elements (store operation) takes place automatically at power-down (except for cy14x101j1). on power-up, data is restored to the sram from the nonvolatile memory (recall operation). the store and recall operations can also be initiated by the user through i 2 c commands. configuration feature cy14x101j1 cy14x101j2 cy14x101j3 autostore no yes yes software store yes yes yes hardware store no no yes notes 1. the i 2 c nvsram is a single solution which is usabl e for all four speed modes of operation. as a result, some i/o parameters are sligh tly different than those on chips which support only one mode of operation. refer to an87209 for more details. 2. serial (i 2 c) nvsram is referred to as nvsram throughout the datasheet. serial number 8 x 8 manufacturer id / product id memory control register command register i c control logic slave address decoder power control block control registers slave memory address and data control quantum trap 128 k x 8 sram 128 k x 8 store sda scl a2, a 1 wp v cc v cap recall sleep 2 memory slave logic block diagram not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 2 of 31 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 i2c interface ...................................................................... 4 protocol overview ............................................................ 4 i2c protocol ? data transfer ....................................... 4 data validity ................................................................ 5 start condition (s) ................................................... 5 stop condition (p) ..................................................... 5 repeated start (sr) ................................................. 5 byte format ................................................................. 5 acknowledge / no-acknowledge ................................. 5 high-speed mode (hs-mode) ..................................... 6 slave device address ......... ........................................ 7 write protection (wp) .................................................. 9 autostore operation .................................................... 9 hardware store and hsb pin operation ................. 9 hardware recall (power-up) .................................. 9 write operation ......................................................... 10 read operation ......................................................... 10 memory slave access ............................................... 10 control registers slave ............................................. 14 write control registers ............................................. 14 serial number ................................................................. 16 serial number write .................................................. 16 serial number lock ................................................... 16 serial number read .................................................. 16 device id ......................................................................... 17 executing commands using command register ..... 17 maximum ratings ........................................................... 18 operating range ............................................................. 18 dc electrical characteristics ........................................ 18 data retention and endurance ..................................... 19 thermal resistance ........................................................ 19 ac test loads and waveforms ..................................... 20 ac test conditions ........................................................ 20 ac switching characteristics ....................................... 21 switching waveforms .................................................... 21 nvsram specifications ................................................. 22 switching waveforms .................................................... 22 software controlled store/recall cycles .............. 23 switching waveforms .................................................... 23 hardware store cycle ................................................. 24 switching waveforms .................................................... 24 ordering information ...................................................... 25 ordering code definitions ..... .................................... 25 package diagrams .......................................................... 26 acronyms ........................................................................ 28 document conventions ................................................. 28 units of measure ....................................................... 28 document history page ................................................. 29 sales, solutions, and legal information ...................... 31 worldwide sales and design s upport ......... .............. 31 products .................................................................... 31 psoc? solutions ...................................................... 31 cypress developer community ................................. 31 technical support ................. .................................... 31 not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 3 of 31 pinouts figure 1. 8-pin soic pinout figure 2. 16-pin soic pinout wp scl 1 2 3 4 5 nc 8 7 6 v cc sda a1 a2 v top view not to scale cy14x101j1 ss wp scl 1 2 3 4 5 8 7 6 v cc sda a1 a2 top view not to scale cy14x101j2 v cap v ss [3] wp v cap 1 2 3 4 5 6 7 8 9 10 11 12 13 nc 16 15 14 v cc a2 sda scl a1 hsb nc top view not to scale v ss nc nc nc nc nc cy14x101j3 [3] pin definitions pin name i/o type description scl input clock. runs at speeds up to a maximum of f scl . sda input/output i/o. input/ output of data through i 2 c interface. output: is open-drain and requires an external pull-up resistor. wp input write protect. protects the memory from all wr ites. this pin is internally pulled low and hence can be left open if not connected. a2?a1 input slave address. defines the slave address for i 2 c. this pin is internally pulled low and hence can be left open if not connected. hsb input/output hardware store busy output: indicates busy status of nvsram when low. after each hardwa re and software store operation hsb is driven high for a short time (t hhhd ) with standard output high current and then a weak internal pull-up resistor keeps this pin high (external pull up resist or connection optional). input: hardware store implemented by pulling this pin low externally. v cap power supply autostore capacitor. suppl ies power to the nvsram during power loss to store data from the sram to nonvolatile elements. if not required, autostore must be disabled and this pin left as no connect. it must never be connected to ground. nc no connect no connect. this pin is not connected to the die. v ss power supply ground. v cc power supply power supply. note 3. this pin is reserved for lower densities. not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 4 of 31 i 2 c interface i 2 c bus consists of two lines ? serial clock line (scl) and serial data line (sda) that carry information between multiple devices on the bus. i 2 c supports multi-master and multi-slave configurations. the data is transm itted from the transmitter to the receiver on the sda line and is synchronized with the clock scl generated by the master. the scl and sda lines are open-drain lines and are pulled up to v cc using resistors. the choice of a pull-up resistor on the system depends on the bus capaci tance and the intended speed of operation. the master generates the clock and all the data i/os are transmitted in synchroni zation with this clock. the cy14x101j supports up to 3.4 mhz clock speed on scl line. protocol overview this device supports only a 7-bit addressable scheme. the master generates a start condition to initiate the communication followed by broadcasting a slave select byte. the slave select byte consists of a seven bit address of the slave that the master intends to communicate with and r/w bit indicating a read or a write o peration. the selected slave responds to this with an acknowledgement (ack). after a slave is selected, the remaining part of the communication takes place between the master and the sele cted slave device. the other devices on the bus ignore the signals on the sda line till a stop or repeated start condition is detected. the data transfer is done between the master and the selected slave device through the sda pin synchronized with the scl clock generated by the master. i 2 c protocol ? data transfer each transaction in i 2 c protocol starts with the master generating a start condition on the bus, followed by a seven bit slave address and eighth bit (r/w ) indicating a read (1) or a write (0) operation. all signals are transmitted on the open-drain sda line and are synchronized with the clock on scl line. each byte of data transmitted on the i 2 c bus is acknowledged by the receiver by holding the sda line low on the ninth clock pulse. the request for write by the master is followed by the memory address and data bytes on the sda line. the writes can be performed in burst-mode by send ing multiple bytes of data. the memory address increments automatically after receiving /transmitting of each byte on the falling edge of 9 th clock cycle. the new address is latched just prior to sending/receiving the acknowledgment bit. this allows the next sequential byte to be accessed with no additional addressing. on reaching the last memory location, the address rolls back to 0x00000 and writes continue. the slave responds to each byte sent by the master during a write operation with an ack. a write sequence can be terminated by the master generating a stop or repeated start condition. a read request is performed at the current address location (address next to the last location accessed for read or write). the memory slave device responds to a read request by transmitting the data on the current address location to the master. a random address read may also be performed by first sending a write request with the intended addre ss of read. the master must abort the write immediately after the last address byte and issue a repeated start or stop signal to prevent any write operation. the following read oper ation starts from this address. the master acknowledges the receipt of one byte of data by holding the sda pin low for the ninth clock pulse. the reads can be terminated by the master sending a no-acknowledge (nack) signal on the sda line after the last data byte. the no-acknowledge signal causes the cy14x101j to release the sda line and the master can then generate a stop or a repeated start condition to initiate a new operation. figure 3. system configuration using serial (i 2 c) nvsram vcc sda scl vcc vcc 1a 1a 1 a a2 a2 a2 lcs lcs lcs sda ads ads pw pw pw cy14x101j cy14x101j cy14x101j #0 #1 #3 microcontroller r pmin = (v cc - v ol max) / i ol r pmax = t r / (0.8473 * c b ) not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 5 of 31 data validity the data on the sda line must be stable during the high period of the clock. the state of the data line can only change when the clock on the scl line is low for the data to be valid. there are only two conditions under which the sda line may change state with scl line held high, that is, start and stop condition. the start and stop conditions are generated by the master to signal the beginning and end of a communication sequence on the i 2 c bus. start condition (s) a high to low transition on the sda line while scl is high indicates a start condition. every transaction in i 2 c begins with the master generating a start condition. stop condition (p) a low to high transition on the sda line while scl is high indicates a stop condition. this condition indicates the end of the ongoing transaction. start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again after the stop condition. repeated start (sr) if an repeated start condition is generated instead of a stop condition the bus continues to be busy. the ongoing transaction on the i 2 c lines is stopped and the bus waits for the master to send a slave id for communication to restart. byte format each operation in i 2 c is done using 8 bit words. the bits are sent in msb first format on sda line and each byte is followed by an ack signal by the receiver. an operation continues till a nack is sent by the receiver or stop or repeated start condition is generated by the master the sda line must remain stable when the clock (scl) is high except for a start or stop condition. acknowledge / no-acknowledge after transmitting one byte of da ta or address, the transmitter releases the sda line. the receiver pulls the sda line low to acknowledge the receipt of the byte. every byte of data transferred on the i 2 c bus needs to be responded with an ack signal by the receiver to contin ue the operation. failing to do so is considered as a nack state. nack is the state where receiver does not acknowledge the receipt of data and the operation is aborted. nack can be generated by master during a read operation in following cases: the master did not receive valid data due to noise the master generates a nack to abort the read sequence. after a nack is issued by the master, nvsram slave releases control of the sda pin and the master is free to generate a repeated start or stop condition. nack can be generated by nvsram slave during a write operation in following cases: nvsram did not receive valid data due to noise. the master tries to access writ e protected locations on the nvsram. master must restart the communication by generating a stop or repeated start condition. figure 4. start and stop conditions full pagewidth sda scl p stop condition sda scl s start condition figure 5. data transfer on the i 2 c bus handbook, full pagewidth sr or p sda sr p scl stop or repeated start condition s or sr start or repeated start condition 1 2 3 - 8 9 ack 9 ack 78 12 msb acknowledgement signal from slave byte complete, interrupt within slave clock line held low while interrupts are serviced acknowledgement signal from receiver not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 6 of 31 high-speed mode (hs-mode) in hs-mode, nvsram can transf er data at bit rates of up to 3.4 mbit/s. a master code (0000 1xxxb) must be issued to place the device into high speed mode. this enables master slave communication for speed upto 3.4 mhz. a stop condition exits hs-mode. serial data format in hs-mode serial data transfer format in hs-mode meets the standard-mode i 2 c-bus specification. hs-mode can only commence after the following conditions (all of which are in f/s-modes): 1. start condition (s) 2. 8-bit master code (0000 1xxxb) 3. no-acknowledge bit (a ) single and multiple-byte reads and writes are supported. after the device enters into hs-mode, data transfer continues in hs-mode until stop condition is se nt by master device. the slave switches back to f/s-mode after a stop condition (p). to continue data transfer in hs-mode, the master sends repeated start (sr). see figure 13 on page 11 and figure 16 on page 12 for hs-mode timings for read and write operation. figure 6. acknowledge on the i 2 c bus handbook, full pagewidth s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge (a) acknowledge (a) data output by master data output by slave scl from master figure 7. data transfer format in hs-mode handbook, full pagewidth f/s-mode hs-mode f/s-mode aa / a a data n (bytes + ack.) w/r s master code sr slave add. hs-mode continues sr slave add. p not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 7 of 31 slave device address every slave device on an i 2 c bus has a device select address. the first byte after start condition contains the slave device address with which the master intends to communicate. the seven msbs are the device address and the lsb (r/w bit) is used for indicating read or write operation. the cy14x101j reserves two sets of upper 4 msbs [7:4] in the slave device address field for accessing memory and control registers. the accessing mechanism is described in memory slave device . the nvsram product provides two different functionalities: memory and control registers fu nctions (such as serial number and product id). the two functi ons of the device are accessed through different slave device addresses. the first four most significant bits [7:4] in the device address register are used to select between the nvsram functions. memory slave device the nvsram device is select ed for read/write if the master issues the slave address as 1010b followed by two bits of device select. if slave address sent by the master matches with the memory slave device address then depending on the r/w bit of the slave address, data is either read from (r/w = ?1?) or written to (r/w = ?0?) the nvsram. the address length for cy14x101j is 17 bits and thus it requires 3 address bytes to map the entire memory address location. to save an extra byte for memory addressing, the 17 th bit (a16) is mapped to the slave address select bit (a0). the dedicated two address bytes represent bit a0 to a15. control registers slave device the control registers slave device includes the serial number, product id, memory control and command register. the nvsram control register slave device is selected for read/write if the master issues the slave address as 0011b followed by two bits of device select. then, depending on the r/w bit of the slave address, data is either read from (r/w = ?1?) or written to (r/w = ?0?) the device. table 1. slave device addressing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nvsram function select cy14x101j slave devices 1 0 1 0 device select id a16 r/w selects memory memory, 128 k 8 0 0 1 1 device select id x r/w selects control registers control registers - memory control register, 1 8 - serial number, 8 8 - device id, 4 8 - command register, 1 8 figure 8. memory slave device address handbook, halfpage r/w lsb msb slave id 10 1 0 a2 a16 a1 device select msb of address figure 9. control registers slave device address table 2. control registers map address description read/write details 0x00 memory control register read/write contains block protect bits and serial number lock bit 0x01 serial number 8 bytes read/write (read only when snl is set) programmable serial number. locked by setting the serial number lock bit in the memory control register to ?1?. 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 device id read only device id is factory programmed 0x0a 0x0b 0x0c 0x0d reserved reserved reserved handbook, halfpage r/w lsb msb slave id 00 1 1 a2 x a1 device select not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 8 of 31 memory control register the memory control register contains the following bits: bp1:bp0 : block protect bits are used to protect 1/4, 1/2 or full memory array. these bits can be written through a write instruction to the 0x00 location of the control register slave device. however, any store cycle causes transfer of sram data into a nonvolatile cell regardless of whether or not the block is protected. the default value shipped from the factory for bp0 and bp1 is ?0?. snl (s/n lock) bit : serial number lock bit (snl) is used to lock the serial number. once the bit is set to ?1?, the serial number registers are locked and no modification is allowed. this bit cannot be cleared to ?0?. the serial number is secured on the next store operation (software store or autostore). if autostore is not enabled, user must perform the software store operation to secure the lock bit status. if a store was not performed, the serial number lock bit will not survive the power cycle. the default value shipped from the factory for snl is ?0?. command register the command register resides at address ?aa? of the control registers slave device. this is a write only register. the byte written to this register initia tes a store, recall, autostore enable, autostore disable and sleep mode operation as listed in ta b l e 5 . refer to serial number on page 16 for details on how to execute a command register byte. store : initiates nvsram software store. the nvsram cannot be accessed for t store time after this instruction has been executed. when initiated, the device performs a store operation regardless of whether a write has been performed since the last nv ope ration. after the t store cycle time is completed, the sram is activated again for read and write operations. recall : initiates nvsram software recall. the nvsram cannot be accessed for t recall time after this instruction has been executed. the recall operation does not alter the data in the nonvolatile elements. a recall may be initiated in two ways: hardware recall, initiated on power-up; and software recall, initiated by a i 2 c recall instruction. asenb : enables nvsram autostore. the nvsram cannot be accessed for t ss time after this instruction has been executed. this setting is not nonvolatile and needs to be followed by a manual store sequence if this is desired to survive the power cycle. the part comes from the factory with autostore enabled and 0x00 written in all cells. asdisb : disables nvsram autostore. the nvsram cannot be accessed for t ss time after this instruction has been executed. this setting is not nonvolatile and needs to be followed by a manual store sequence if this is desired to survive power cycle. note if autostore is disabled and v cap is not required, it is required that the v cap pin is left open. v cap pin must never be connected to ground. power-up recall operation cannot be disabled in any case. sleep : sleep instruction puts the nvsram in a sleep mode. when the sleep instruction is registered, the nvsram takes t ss time to process the sl eep request. once the sleep command is successfully registered and processed, the nvsram toggles hsb low, performs a store operation to secure the data to nonvolatile memory and then enters into sleep mode. whenever nvsram enters into sleep mode, it initiates non volatile store cycle which results in losing an endurance cycle per sleep command execution. a store cycle starts only if a write to the sram has been performed since the last store or recall cycle. the nvsram enters into sleep mode as follows: 1. the master sends a start command 2. the master sends control registers slave device id with i 2 c write bit set (r/w = ?0?) 3. the slave (nvsram) sends an ack back to the master 4. the master sends command register address (0xaa) 0xaa command register write only allows commands for store, recall, autostore enable/disable, sleep mode table 3. memory control register bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0snl (0) 0 0 bp1 (0) bp0 (0) 00 table 4. block protection level bp1:bp0 block protection 00 0n o n e 1/4 01 0x18000?0x1ffff 1/2 10 0x10000?0x1ffff 1 11 0x00000?0x1ffff table 2. control registers map (continued) address description read/write details table 5. command register bytes data byte [7:0] command description 0011 1100 store store sram data to nonvolatile memory 0110 0000 recall recall data from nonvolatile memory to sram 0101 1001 asenb enable autostore 0001 1001 asdisb disable autostore 1011 1001 sleep enter sleep mode for low power consumption not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 9 of 31 5. the slave (nvsram) sends an ack back to the master 6. the master sends command register byte for entering into sleep mode 7. the slave (nvsram) sends an ack back to the master 8. the master generates a stop condition. once in sleep mode the device starts consuming i zz current t sleep time after sleep instruction is registered. the device is not accessible for normal operations until it is out of sleep mode. the nvsram wakes up after t wake duration after the device slave address is transmitted by the master. transmitting any of the two slave addresses wakes the nvsram from sleep mode. the nvsram device is not accessible during t sleep and t wake interval, and any a ttempt to access the nvsram device by the master is ignored and nvsram sends nack to the master. as an al ternative method of determining when the device is ready, the master can send read or write commands and look for an ack. write protection (wp) the wp pin is an active high pin and protects entire memory and all registers from write operations. to inhibit all the write operations, this pin must be held high. when this pin is high, all memory and register writes are prohibited and address counter is not incremented. this pin is internally pulled low and hence can be left open if not used. autostore operation the autostore operation is a unique feature of nvsram which automatically stores the sram data to quantumtrap cells during power-down. this store makes use of an external capacitor (v cap ) and enables the device to safely store the data in the nonvolatile memory when power goes down. during normal operation, the device draws current from v cc to charge the capacitor connected to the v cap pin. when the voltage on the v cc pin drops below v switch during power-down, the device inhibits all memory accesses to nvsram and automatically performs a conditional store operation using the charge from the v cap capacitor. the autostore operation is not initiated if no write cycle has been performed since the last store or recall. note if a capacitor is not connected to v cap pin, autostore must be disabled by issuing the autostore disable instruction specified in command register on page 8 . if autostore is enabled without a capacitor on v cap pin, the device attempts an autostore operation without suffic ient charge to complete the store. this will corrupt the data stored in nvsram as well as the serial number and it will unlock the snl bit. figure 10 shows the proper connection of the storage capacitor (v cap ) for autostore operation. refer to dc electrical characteristics on page 18 for the size of the v cap . figure 10. autostore mode hardware store and hsb pin operation the hsb pin in cy14x101j is used to control and acknowledge store operations. if no store or recall is in progress, this pin can be used to request a ha rdware store cycle. when the hsb pin is driven low, the device conditionally initiates a store operation after t delay duration. an actual store cycle starts only if a write to the sram has been performed since the last store or recall cycle. re ads and writes to the memory are inhibited for t store duration or as long as hsb pin is low. the hsb pin also acts as an open drain driver (internal 100 k ? weak pull-up resistor) that is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. note after each hardware and software store operation hsb is driven high for a short time (t hhhd ) with standard output high current and then remains high by internal 100 k ? pull-up resistor. note for successful last data byte store, a hardware store should be initiated at least one cl ock cycle after the last data bit d0 is received. upon completion of the store operation, the nvsram memory access is inhibited for t lzhsb time after hsb pin returns high. leave the hsb pin unconnected if not used. hardware recall (power-up) during power-up, when v cc crosses v switch , an automatic recall sequence is initiated which transfers the content of nonvolatile memory on to the sram. the data would previously have been stored on the nonvolatile memory through a store sequence. a power-up recall cycle takes t fa time to complete and the memory access is disabled during this time. hsb pin can be used to detect the ready status of the device. 0.1 uf v cc v cap v cap v ss v cc not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 10 of 31 write operation the last bit of the slave device a ddress indicates a read or a write operation. in case of a write operation, the slave device address is followed by the memory or register address and data. a write operation continues as long as a stop or repeated start condition is generated by the mast er or if a nack is issued by the nvsram. a nack is issued from the nvsram under the following conditions: 1. a valid device id is not received. 2. a write (burst write) access to a protected memory block address returns a nack from nvsram after the data byte is received. however, the address counter is set to this address and the following current read operation starts from this address. 3. a write/random read access to an invalid or out-of-bound memory address returns a nack from the nvsram after the address is received. the address counter remains unchanged in such a case. after a nack is sent out from the nvsram, the write operation is terminated and any data on the sda line is ignored till a stop or a repeated start condition is generated by the master. for example, consider a case where the burst write access is performed on control register slave address 0x01 for writing the serial number and continued to the address 0x09, which is a read only register. the device returns a nack and address counter will not be incremented. a following read operation will be started from the address 0x09. further, any write operation which starts from a write protected address (say, 0x09) will be responded by the nvsram with a nack after the data byte is sent and set the address counter to this address. a following read operation will start from the address 0x09 in this case also. note in case the user tries to read/write access an address that does not exist (for example 0x0d in control register slave), nvsram responds with a nack immediately after the out-of-bound address is transmitted. the address counter remains unchanged and holds the previous successful read or write operation address. a write operation is performed internally with no delay after the eighth bit of data is transmitt ed. if a write operation is not intended, the master must term inate the write operation before the eighth clock cycle by generating a stop or repeated start condition. more details on write instructio n are provided in the section memory slave access. read operation if the last bit of the slave device address is ?1?, a read operation is assumed and the nvsram takes control of the sda line immediately after the slave device address byte is sent out by the master. the read operation starts from the current address location (the location following the previous successful write or read operation). when the last address is reached, the address counter loops back to the first address. in case of the control register slave, whenever a burst read is performed such that it flows to a non-existent address, the reads operation will loop back to 0x00. this is applicable, in particular for the command register. there are the following ways to end a read operation: 1. the master issues a nack on the 9th clock cycle followed by a stop or a repeated start condition on the 10th clock cycle. 2. master generates a stop or repeated start condition on the 9 th clock cycle. more details on write instruct ion are provided in the section memory slave access . memory slave access the following sections describe the data transfer sequence required to perform read or write operations from nvsram. write nvsram each write operation consists of a slave address being transmitted after the start conditi on. the last bit of slave address must be set as ?0? to indicate a write operation. the master may write one byte of data or continue writing multiple consecutive address locations while the internal address counter keeps incrementing automatically. the address register is reset to 0x00000 after the last address in memory is accessed. the write operation continues till a stop or repeated start condition is generated by the master or a nack is issued by the nvsram. a write operation is executed onl y after all the 8 data bits have been received by the nvsram. the nvsram sends an ack signal after a successful write op eration. a writ e operation may be terminated by the master by generating a stop condition or a repeated start operation. if the master desires to abort the current write operation without altering the memory contents, this should be done using a start/stop condition prior to the 8th data bit. if the master tries to access a write protected memory address on the nvsram, a nack is returned after the data byte intended to write the protected address is transmitted and address counter will not be incremented. similarly, in a burst mode write operation, a nack is returned when the data byte that attempts to write a protected memory lo cation and the address counter will not be incremented. not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 11 of 31 figure 11. single-byte write into nvsram (except hs-mode) s10 1 0 a2 a1 a16 0 a a a a s t a r t s t 0 p p most signifiant address byte least significant address byte data byte memory slave address sda line by master by nvsram figure 12. multi-byte write into nvsram (except hs-mode) s10 1 0 a2 a1 a16 0 a a a a s t a r t most significant address byte memory slave address sda line by master a s t 0 p p data byte n ~ ~ by nvsram data byte 1 least significant address byte figure 13. single-byte write into nvsram (hs-mode) s10 1 0 a2 a1 a16 0 a a a a s t a r t most significant address byte memory slave address sda line by master a s t 0 p p data byte n ~ ~ by nvsram data byte 1 least significant address byte figure 14. multi-byte write into nvsram (hs-mode) s00 0 0 1x x x a a a a s t a r t memory slave address most significant address byte least significant address byte hs-mode command sda line by master a data byte 1 sr 10 10 a2 a1 a16 0 a data byte 2 ~ ~ a data byte 3 a s t 0 p p data byte n ~ ~ by nvsram sda line by master by nvsram not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 12 of 31 current nvsram read each read operation starts with the master transmitting the nvsram slave address with the lsb set to ?1? to indicate ?read?. the reads start from the address on the address counter. the address counter is set to the address location next to the last accessed with a ?write? or ?read? operation. the master may terminate a read operation after reading 1 byte or continue reading addresses sequentially till the last address in the memory after which the addre ss counter roll s back to the address 0x00000. the valid methods of terminating read access are described in the section read operation on page 10 . note a16-bit is ignored while using the current nvsram read. figure 15. current location single-byte nvsram read (except hs-mode) figure 16. current location multi- byte nvsram read (except hs-mode) figure 17. current location single-byte nvsram read (hs-mode) figure 18. current location multi-byte nvsram read (hs-mode) s1 0 1 0 a2 a1 x 1 a a s t a r t s t 0 p p data byte memory slave address sda line by master by nvsram s10 1 0 a2 a1 x 1 a a a s t a r t s t 0 p p data byte data byte n memory slave address sda line by master ~ ~ by nvsram s00 0 0 1x x x a a s t a r t memory slave address hs-mode command sda line by master s t 0 p p sr 10 10 a2 a1 x 1 a by nvsram data byte s00 0 0 1x x x a a a s t a r t memory slave address hs-mode command sda line by master s t 0 p p sr 10 10 a2 a1 x 1 a by nvsram data byte data byte n not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 13 of 31 random address read a random address read is performed by first initiating a write operation and generating a repeated start immediately after the last address byte is acknowledged. the address counter is set to this address and the next read access to this slave will initiate read operation from here. the master may terminate a read operation after reading 1 byte or continue reading addresses sequentially till the la st address in the memory after which the address counter rolls back to the start address 0x00000. figure 19. random address single-byte read (except hs-mode) figure 20. random address multi-byte read (except hs-mode) figure 21. random address single-byte read (hs-mode) s10 1 0 a2 a1 a16 0 a a a a s t a r t most significant address byte least significant address byte memory slave address memory slave address sda line by master a s t 0 p p 1 01 0 a2 a1 x 1 sr by nvsram data byte s10 1 0 a2 a1 a16 0 a a a a s t a r t most significant address byte least significant address byte memory slave address memory slave address sda line by master a 1 01 0 a2 a1 x 1 sr a s t 0 p p ~ ~ by nvsram data byte 1 data byte n s00 0 0 1x x x a a s t a r t memory slave address hs-mode command sda line by master most significant address byte sr 10 10 a2 a1 a16 0 least significant address byte a memory slave address a sr 1 0 1 0 a2 a1 x 1 s t 0 p p data byte a 0 ~ ~ a by nvsram not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 14 of 31 control registers slave the following sections describes the data transfer sequence required to perform read or write operations from control registers slave. write control registers to write the control registers sl ave, the master transmits the control registers slave address after generating the start condition. the write sequenc e continues from the address location specified by the master till the master generates a stop condition or the last writable address location. if a non writable address location is accessed for write operation during a normal write or a burst, the slave generates a nack after the data byte is sent and the write sequence terminates. any following data bytes are ignored and the address counter is not incremented. if a write operation is performed on the command register (0xaa), the following current read operation also begins from the first address (0x00) as in this case, the current address is an out-of-bound address. the address is not incremented and the next current read operation begins from this address location. if a write operation is attemp ted on an out-of-bound address location, the nvsram sends a nack immediately after the address byte is sent. further, if the serial number is locked, only two addresses (0xaa or command register, and 0x00 or memory control register) are writable in the control regist ers slave. on a write operation to any other address location, the device will acknowledge command byte and address bytes but it returns a nack from the control registers slave for data bytes. in this case, the address will not be incremented and a current read will happen from the last acknowledged address. the nvsram control registers slave sends a nack when an out of bound memory address is accessed for write operation, by the master. in such a case, a following current read operation begins from the last acknowledged address. figure 22. random address multi-byte read (hs-mode) s00 0 0 1x x x a a s t a r t memory slave address hs-mode command sda line by master most significant address byte sr 10 10 a2 a1 a16 0 least significant address byte a memory slave address a sr 1 0 1 0 a2 a1 x 1 data byte a ~ ~ s t 0 p p data byte n a ~ ~ by nvsram a figure 23. single-byte write into control registers s00 1 1 a2 a1 x 0 a a a s t a r t s t 0 p p control register address data byte control registers slave address sda line by master by nvsram figure 24. multi-byte write into control registers s00 1 1 a2 a1 x 0 a a a a s t a r t s t 0 p p control register address data byte data byte n control registers slave address sda line by master ~ ~ by nvsram not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 15 of 31 current control registers read a read of control registers slave is started with master sending the control registers slave address after the start condition with the lsb set to ?1?. the reads begin from the current address which is the next address to the last accessed location. the reads to control registers slave continues till the last readable address location and loops back to the first location (0x00). note that the command register is a write only register and is not accessible through the sequential read operations. if a burst read operation begins from the command register (0xaa), the address counter wraps around to the first address in the register map (0x00). random control registers read a read of random address may be performed by initiating a write operation to the intended location of read and immediately following with a repeated start operation. the reads to control registers slave continues till the last readable address location and loops back to the first location (0x00). note that the command register is a write only register and is not accessible through the sequential read operat ions. a random read starting at the command register (0xaa) loops back to the first address in the control registers register map (0x00). if a random read operation is initiated from an out-of-bound memory address, the nvsram sends a nack after the address byte is sent. . figure 25. control registers single-byte read s00 1 1 a2 a1 x 1 a a s t a r t s t 0 p p data byte control registers slave address sda line by master by nvsram figure 26. current control registers multi-byte read s00 1 1 a2 a1 x 1 a a s t a r t s t 0 p p data byte data byte n control registers slave address sda line by master by nvsram a ~ ~ figure 27. random control registers single-byte read s00 1 1 a2 a1 x 0 a a a a s t a r t s t 0 p p control register address control registers slave address data byte control registers slave address sda line by master sr 0 0 1 1 a2 a1 x 1 by nvsram not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 16 of 31 serial number serial number is an 8 byte memory space provided to the user to uniquely identify th is device. it typically consists of a two byte customer id, followed by five bytes of unique serial number and one byte of crc check. however, nvsram does not calculate the crc and it is up to the user to utilize the eight byte memory space in the desired format. the default values for the eight byte locations are set to ?0x00?. serial number write the serial number can be accessed through the control registers slave device. to wr ite the serial number, master transmits the control registers slave address after the start condition and writes to the address location from 0x01 to 0x08. the content of serial number registers is secured to nonvolatile memory on the next store operation. if autostore is enabled, nvsram automatically stores the serial number in the nonvolatile memory on power-down. however, if autostore is disabled, user must perform a store operation to secure the contents of serial number registers. note if the serial number lock (snl) bit is not set, the serial number registers can be re-written regardless of whether or not a store has happened. once the serial number lock bit is set, no writes to the serial number r egisters are allowed. if the master tries to perform a write operation to the serial number registers when the lock bit is set, a nack is returned and write will not be performed. serial number lock after writes to serial number registers is complete, master is responsible for locking the serial number by setting the serial number lock bit to ?1? in the memory control register (0x00). the content of memory control register and serial number are secured on the next store operation (store or autostore). if autostore is not enabled, user must perform store operation to secure the lock bit status. if a store was not performed, the serial number lock bit will not survive the power cycle. the seri al number lock bit and 8 - byte serial number is defaults to ?0? at power-up. serial number read serial number can be read back by a read operation of the intended address of the control registers slave. the control registers device loops back from the last address (excluding the command register) to 0x00 address location while performing burst read operation. the serial number resides in the locations from 0x01 to 0x08. even if the serial number is not locked, a serial number read operation will return the current values written to the serial number register s. master may perform a serial number read operation to confirm if the correct serial number is written to the registers before setting the lock bit. figure 28. random control registers multi-byte read s00 1 1 a2 a1 x 0 a a a s t a r t control register address control registers slave address data byte control registers slave address sda line by master sr 0 0 1 1 a2 a1 x 1 a s t 0 p p data byte n a ~ ~ by nvsram not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 17 of 31 device id device id is a 4 byte code consisting of jedec assigned manufacturer id, product id, density id, and die revision. these regist ers are set in the factory and are r ead only registers for the user. the device id is divided into four parts as shown in table 6 : 1. manufacturer id (11 bits) this is the jedec assigned manufacturer id for cypress. jedec assigns the manufacturer id in different banks. the first three bits of the manufacturer id represent the bank in which id is assigned. the next eight bits represent the manufacturer id. cypress manufacturer id is 0x34 in bank 0. therefore the manufacturer id for all cypress nvsram products is given as: cypress id - 000_0011_0100 2. product id (14 bits) the product id for device is shown in the ta b l e 6 . 3. density id (4 bits) the 4 bit density id is used as shown in table 6 for indicating the 1 mb density of the product. 4. die rev (3 bits) this is used to represent any major change in the design of the product. the initial setting of this is always 0x0. executing commands using command register the control registers slave allows different commands to be executed by writing the specific command byte in the command register (0xaa). the command byte codes for each command are specified in table 5 on page 8 . during the execution of these commands the device is not accessible and returns a nack if any of the three slave devices is selected. if an invalid command is sent by the master, the nvsram responds with an ack indicating that the command has been acknowledged with nop (no operation). the address will rollover to 0x00 location. figure 29. command execution using command register table 6. device id device device id (4 bytes) device id description 31?21 (11 bits) 20?7 (14 bits) 6?3 (4 bits) 2?0 (3 bits) manufacture id product id density id die rev cy14c101j1 0x068120a0 00000110100 00001001000001 0100 000 cy14c101j2 0x0681a0a0 00000110100 00001101000001 0100 000 cy14c101j3 0x0681a2a0 00000110100 00001101000101 0100 000 cy14b101j1 0x068128a0 00000110100 00001001010001 0100 000 cy14b101j2 0x0681a8a0 00000110100 00001101010001 0100 000 cy14b101j3 0x0681aaa0 00000110100 00001101010101 0100 000 cy14e101j1 0x068130a0 00000110100 00001001100001 0100 000 cy14e101j2 0x0681b0a0 00000110100 00001101100001 0100 000 cy14e101j3 0x0681b2a0 00000110100 00001101100101 0100 000 s00 1 1 a2 a1 x 0 a a s t a r t command register address command byte control register slave address sda line by master a 1 0 0 0 0 1 1 1 by nvsram p s t o p not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 18 of 31 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c maximum accumulated storage time at 150 c ambient temperature ...................... 1000 h at 85 c ambient temperature ..................... 20 years maximum junction temperature ................................. 150 c supply voltage on v cc relative to v ss cy14c101j: ....................... ..............?0.5 v to +3.1 v cy14b101j: ......................................?0.5 v to +4.1 v cy14e101j: ......................................?0.5 v to +7.0 v dc voltage applied to outputs in high z state .................................... ?0.5 v to v cc + 0.5 v input voltage ....................................... ?0.5 v to v cc + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ................. ?2.0 v to v cc + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount lead soldering temperature (3 seconds) ........... ............................ .. +260 c dc output current (1 output at a time, 1s duration). .... 15 ma static discharge voltage (per mil-std-883, method 3015) .............. ........... > 2001 v latch up current .................................................... > 140 ma operating range product range ambient temperature v cc cy14c101j industrial ?40 c to +85 c 2.4 v to 2.6 v cy14b101j 2.7 v to 3.6 v cy14e101j 4.5 v to 5.5 v dc electrical characteristics over the operating range parameter description test conditions min typ [4] max unit v cc power supply cy14c101j 2.4 2.5 2.6 v cy14b101j 2.7 3.0 3.6 v cy14e101j 4.5 5.0 5.5 v i cc1 average v cc current f scl = 3.4 mhz; values obtained without output loads (i out = 0 ma) ??1ma f scl = 1 mhz; values obtained without output loads (i out = 0 ma) cy14c101j cy14b101j ??400 ? a cy14e101j ? ? 450 ? a i cc2 average v cc current during store all inputs don?t care, v cc = max average current for duration t store ??3m a i cc4 average v cap current during autostore cycle all inputs don?t care. average current for duration t store ??3m a i sb v cc standby current scl > (v cc ? 0.2 v). v in < 0.2 v or > (v cc ? 0.2 v). standby current level after nonvolatile cycle is complete. inputs are static. f scl = 0 mhz. ??150 ? a i zz sleep mode current t sleep time after sleep instruction is issued. all inputs are static and configured at cmos logic level. ??8 ? a i ix [5] input current in each i/o pin (except hsb ) 0.1 v cc < v i < 0.9 v cc(max) ?1 ? +1 ? a input current in each i/o pin (for hsb ) ?100 ? +1 ? a i oz output leakage current ?1 ? +1 ? a c i capacitance for each i/o pin capacitance measured across all input and output signal pin and v ss . ??7pf notes 4. typical values are at 25 c, v cc = v cc(typ) . not 100% tested. 5. not applicable to wp, a2 and a1 pins. not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 19 of 31 v ih input high voltage 0.7 vcc ? v cc + 0.5 v v il input low voltage ? 0.5 ? 0.3 vcc v v ol output low voltage i ol = 3 ma 0 ? 0.4 v i ol = 6 ma 0 ? 0.6 v r in [6] input resistance (wp, a2, a1) for v in = v il (max) 50 ? ? k ? for v in = v ih (min) 1??m ? v hys hysteresis of schmitt trigger inputs 0.05 v cc ??v v cap [7] storage capacitor between v cap pin and v ss cy14c101j 170 220 270 ? f cy14b101j cy14e101j 42 47 180 ? f v vcap [8, 9] maximum voltage driven on v cap pin by the device v cc = max cy14c101j cy14b101j ??v cc v cy14e101j ? ? v cc ? 0.5 v dc electrical characteristics (continued) over the operating range parameter description test conditions min typ [4] max unit data retention and endurance over the operating range parameter description min unit data r data retention 20 years nv c nonvolatile store operations 1,000 k thermal resistance parameter [9] description test conditions 8-pin soic 16-pin soic unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 101.08 56.68 ?c/w ? jc thermal resistance (junction to case) 37.86 32.11 ?c/w notes 6. the input pull-down circuit is stronger (50 k ? ) when the input voltage is below v il and weak (1 m ? ) when the input voltage is above v ih . 7. min v cap value guarantees that there is a sufficient charge avail able to complete a successful autostore operation. max v cap value guarantees that the capacitor on v cap is charged to a minimum voltage during a power-up recall cycle so that an immediate power-down cycle can complete a successful autostore. therefore it is always recommended to use a capacitor within the specified min and max limits. refer application note an43593 for more details on v cap options. 8. maximum voltage on v cap pin (v vcap ) is provided for guidance when choosing the v cap capacitor. the voltage rating of the v cap capacitor across the operating temperature range should be higher than the v vcap voltage. 9. these parameters are guaranteed by design and are not tested. not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 20 of 31 ac test loads and waveforms figure 30. ac test loads and waveforms 2.5 v output 100 pf 700 ? for 2.5 v (cy14c101j) 3.0 v output 100 pf 867 ? for 3.0 v (cy14b101j) 5.0 v output 50 pf 1.6 k ? for 5.0 v (cy14e101j) ac test conditions cy14c101j cy14b101j cy14e101j input pulse levels 0 v to 2.5 v 0 v to 3 v 0 v to 5 v input rise and fall times (10%?90%) 10 ns 10 ns 10 ns input and output timing reference levels 1.25 v 1.5 v 2.5 v not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 21 of 31 ac switching characteristics over the operating range parameter [10] description 3.4 mhz [11] 1 mhz [11] 400 khz [11] unit min max min max min max f scl clock frequency, scl ? 3400 ? 1000 ? 400 khz t su; sta setup time for repeated start condition 160 ? 250 ? 600 ? ns t hd;sta hold time for start condition 160 ? 250 ? 600 ? ns t low low period of the scl 160 ? 500 ? 1300 ? ns t high high period of the scl 60 ? 260 ? 600 ? ns t su;data data in setup time 10 ? 100 ? 100 ? ns t hd;data data hold time (in/out) 0 ? 0 ? 0 ? ns t dh data out hold time 0 ? 0 ? 0 ? ns t r [12] rise time of sda and scl ? 80 ? 120 ? 300 ns t f [12] fall time of sda and scl ? 80 ? 120 ? 300 ns t su;sto setup time for stop condition 160 ? 250 ? 600 ? ns t vd;data data output valid time ? 130 ? 400 ? 900 ns t vd;ack ack output valid time ? 130 ? 400 ? 900 ns t of [12] output fall time from v ih(min) to v il(max) ?80?120?250ns t buf bus free time between stop and next start condition 0.3?0.5?1.3?s t sp pulse width of spikes that must be suppressed by input filter ?10?50?50ns switching waveforms figure 31. ti ming diagram ~ ~ ~ ~ s sr t su;sto t su;sta t hd;sta t high t low t su;data t hd;data sda scl p s t buf t sp t hd;sta ~ ~ ~ ~ ~ ~ ~ ~ t r t f t f t r t vd;dat t vd;ack start condition repeated start condition stop condition 9th clock (ack) start condition ~ ~ ~ ~ ~ ~ notes 10. test conditions assume signal transition time of 10 ns or less, timing reference levels of v cc /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol and load capacitance shown in figure 30 on page 20 . 11. bus load (cb) considerations; cb < 500 pf for i 2 c clock frequency (scl) 100/400 khz; cb < 550 pf for scl at 1000 khz; cb < 100 pf for scl at 3.4 mhz. 12. these parameters are guaranteed by design and are not tested. not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 22 of 31 nvsram specifications over the operating range parameter description min max unit t fa [13] power-up recall duration cy14c101j ?4 0m s cy14b101j ?2 0m s cy14e101j ?2 0m s t store [14] store cycle duration ? 8 ms t delay [15] time allowed to complete sram write cycle ? 25 ns t vccrise [16] v cc rise time 150 ? s v switch low voltage trigger level cy14c101j ?2.35v cy14b101j ?2.65v cy14e101j ?4.40v t lzhsb [16] hsb high to nvsram active time ? 5 s v hdis [16] hsb output disable voltage ? 1.9 v t hhhd [16] hsb high active time ? 500 ns t wake time for nvsram to wake up from sleep mode cy14c101j ?4 0m s cy14b101j ?2 0m s cy14e101j ?2 0m s t sleep time to enter low power mode after issuing sleep instruction ? 8 ms t sb [16] time to enter into standby mode after issuing stop condition ? 100 s switching waveforms figure 32. autostore or power-up recall [17] v switch v hdis t vccrise t store t store t hhhd t hhhd t delay t delay t lzhsb t lzhsb t fa t fa hsb out autostore power- up recall read & write inhibited (rwi) power-up recall read & write brown out autostore power-up recall read & write power down autostore note note note note v cc 14 14 18 18 notes 13. t fa starts from the time v cc rises above v switch . 14. if an sram write has not taken place since the last nonvolatile cycle, no autostore or hardware store takes place. 15. on a hardware store and autostore initiation, sram write operation continues to be enabled for time t delay . 16. these parameters are guaranteed by design and are not tested. 17. read and write cycles are ignored during store, recall, and while v cc is below v switch . 18. during power-up and power-down, hsb glitches when hsb pin is pulled up through an external resistor. not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 23 of 31 software controlled store/recall cycles over the operating range parameter description cy14x101j unit min max t recall recall duration ? 600 s t ss [19, 20] software sequence processing time ? 500 s switching waveforms figure 33. software store/recall cycle figure 34. autostore enable/disable cycle s start condition 9 8 2 1 acknowledge (a) by slave data output by master scl from master 9 8 2 1 9 8 2 1 nvsram control slave address command reg address command byte (store/recall) p store / t rwi acknowledge (a) by slave acknowledge (a) by slave t recall s start condition 9 8 2 1 acknowledge (a) by slave data output by master scl from master 9 8 2 1 9 8 2 1 nvsram control slave address command reg address command byte (asenb/asdisb) p ss t rwi acknowledge (a) by slave acknowledge (a) by slave notes 19. this is the amount of time it takes to take action on a soft sequence command. v cc power must remain high to effectively register command. 20. commands such as store and recall lock out i/o until operation is complete which further increases this time. see the specif ic command. not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 24 of 31 hardware store cycle over the operating range parameter description cy14x101j unit min max t phsb hardware store pulse width 15 ? ns switching waveforms figure 35. hardware store cycle [21] ~ ~ hsb (in) hsb (out) rwi hsb (in) hsb (out) rwi t hhhd t store t phsb t delay t lzhsb t delay t phsb hsb pin is driven high to v cc only by internal 100 k: resistor, hsb driver is disabled sram is disabled as long as hsb (in) is driven low. write latch not set write latch set ~ ~ ~ ~ ~ ~ note 21. if an sram write has not taken place since the last nonvola tile cycle, autostore or hardware store is not initiated. not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 25 of 31 ordering code definitions ordering information ordering code package diagram package type operating range cy14b101j1-sxit 51-85066 8-p in soic (without v cap ) industrial cy14b101j1-sxi cy14b101j2-sxit 8-pin soic (with v cap ) cy14b101j2-sxi CY14E101J2-SXIT cy14e101j2-sxi all these parts are pb-free. this table contains final informati on. contact your local cypress sales representative for availab ility of these parts. option: t - tape and reel blank - std. density: 101 - 1 mb cypress cy 14 b 101 j 1 - s x i t 14 - nvsram package: s - 8-pin soic temperature: i - industrial (?40 to 85 c) j - serial (i 2 c) nvsram sf - 16-pin soic voltage: c - 2.5 v b - 3.0 v e - 5.0 v 1 - without v cap 2 - with v cap 3 - with v cap and hsb pb-free not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 26 of 31 package diagrams figure 36. 8-pin soic (150 mils) s0 815/sz815/sw815 packa ge outline, 51-85066 51-85066 *f not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 27 of 31 figure 37. 16-pin soic (0.413 0.299 0.0932 inches) package outline, 51-85022 package diagrams (continued) 51-85022 *e not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 28 of 31 acronyms document conventions units of measure acronym description ack acknowledge cmos complementary metal oxide semiconductor crc cyclic redundancy check eia electronic industries alliance i 2 c inter-integrated circuit i/o input/output jedec joint electron devices engineering council lsb least significant bit msb most significant bit nvsram nonvolatile static random access memory nack no acknowledge rohs restriction of hazardous substances r/w read/write rwi read and write inhibit scl serial clock line sda serial data access snl serial number lock soic small outline integrated circuit sram static random access memory wp write protect symbol unit of measure c degree celsius hz hertz khz kilohertz k? kilohm mbit megabit mhz megahertz m? megaohm ? a microampere ? f microfarad ? s microsecond ma milliampere ms millisecond ns nanosecond ? ohm % percent pf picofarad v volt w watt not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 29 of 31 document history page document title: cy14c101j, cy14b101j, cy 14e101j, 1-mbit (128 k 8) serial (i 2 c) nvsram document number: 001-54050 rev. ecn no. submission date orig. of change description of change ** 2754627 08/21/09 gvch new data sheet. *a 2860397 01/20/2010 gvch updated features (added 3.4 mhz bus frequency related information, changed v cc range for cy14c101j from 2.3 v?2.7 v to 2.4 v?2.6 v, removed 16-pin soic 150 mil package option and added 16-pin soic 300 mil package option). updated dc electrical characteristics (changed i ol min value from 20 ma to 3 ma) updated ac switching characteristics (added 3.4 mhz bus frequency related information, changed minimum value of t low parameter from 400 ns to 500 ns for 1 mhz, changed minimum value of t low parameter from 600 ns to 1300 ns for 400 khz, changed minimum value of t high parameter from 400 ns to 260 ns for 1 mhz, changed minimum value of t dh parameter from 50 s to 0 ns for both 1 mhz and 400 khz, changed maximum value of t r parameter from 100 ns to 120 ns for 1 mhz, changed maximum value of t r parameter from 250 ns to 300 ns for 400 khz, changed maximum value of t f parameter from 100 ns to 120 ns for 1 mhz, changed maximum value of t f parameter from 250 ns to 300 ns for 400 khz, removed minimum value of t sp parameter). *b 2963131 06/28/2010 gvch changed datasheet st atus from ?advance? to ?preliminary?. updated data sheet title from ? cy14c101j, cy14b101j, cy14e101j 1 mbit (128 k 8) serial (i 2 c) nvsram with real time clock (rtc)? to ?cy14c101j, cy14b101j, cy14e101j, 1-mbit (128 k 8) serial (i 2 c) nvsram?. updated logic block diagram . updated pinouts . updated pin definitions . complete content write. updated dc electrical characteristics (changed maximum value of i cc4 parameter from 2 ma to 3 ma, added i oz and c i parameter and details, removed i ol parameter and details, changed v cap value (minimum value from 100 f to 170 f, typical value from 150 f to 220 f, maximum value from 330 f to 270 f) for v cc = 2.4 v?2.6 v, changed v cap value (minimum value from 40 f to 42 f) for v cc = 2.7 v?3.6 v and v cc = 4.5 v?5.5 v). added data retention and endurance . added thermal resistance . added ac test loads and waveforms . added ac test conditions . updated nvsram specifications (added t fa for v cc = 2.4 v?2.6 v, changed v switch from 4.45 v to 4.40 v for v cc = 4.5 v to 5.5 v, added t wake for v cc = 2.4 v?2.6 v, added t sb parameter). added software controlled store/recall cycles . added hardware store cycle . updated ordering information (updated part numbers). *c 3084950 11/12/2010 gvch updated ac switching characteristics (changed maximum value of t sp parameter from 10 ns to 5 ns for 3.4 mhz). updated software controlled store/recall cycles (changed maximum value of t recall parameter from 300 s to 600 s, changed maximum value of t ss parameter from 200 s to 500 s). added units of measure . *d 3147585 01/19/2011 gvch updated hardware store and hsb pin operation (added more clarity on hsb pin operation). updated nvsram specifications (updated t lzhsb parameter description and fixed typo in figure 32 ). not recommended for new designs
cy14c101j cy14b101j cy14e101j document number: 001-54050 rev. *n page 30 of 31 *e 3191637 03/21/2011 gvch updated autostore operation (description). updated table 6 (product id column). updated dc electrical characteristics (added note 5 ). updated in new template. *f 3248609 05/04/2011 gvch changed stat us from preliminary to final. updated ordering information (updated part numbers). *g 3386961 10/03/2011 gvch updated pin definitions (sda pin description). updated command register (sleep description). updated device id (added device id (4 bytes) column in ta b l e 6 ). updated executing commands using command register (description). updated dc electrical characteristics (added i cc1 parameter value of 400 a for 1 mhz frequency, changed maximum value of i cc2 parameter from 2 ma to 3 ma, removed i cc3 parameter, and added note 7 and referred the note in the v cap parameter). updated ac switching characteristics (added note 10 and referred the note in the parameter column, and updated maximum value of t sp parameter from 5 ns to 10 ns for 3.4 mhz). updated software controlled store/recall cycles (updated figure 33 and figure 34 ). updated package diagrams . *h 3453533 12/02/2011 gvch updated dc electrical characteristics (added maximum value of i cc1 parameter (450 a) for cy14e101j). *i 3668269 07/27/2012 gvch updated dc electrical characteristics (added v vcap parameter and its details, added note 8 and referred the same note in v vcap parameter, also referred note 9 in v vcap parameter). updated ordering information (updated part numbers). *j 3751232 09/21/2012 gvch updated maximum ratings (removed ?ambient temperature with power applied? and added ?maximum junction temperature?). *k 3843302 12/17/2012 gvch updated ordering information (added cy14e101j2-sxi and CY14E101J2-SXIT). *l 3892697 02/15/2013 gvch updated features : added note 1 and referred the same note in ?high speed i 2 c interface?. *m 3984909 04/29/2013 gvch updated features : updated note 1 . updated dc electrical characteristics : added one more condition ?i ol = 6 ma? for v ol parameter and added respective values. updated ac switching characteristics : updated note 11 . changed value of t of parameter from 300 ns to 250 ns for 400 khz frequency. updated package diagrams : spec 51-85066 ? changed revision from *e to *f. spec 51-85022 ? changed revision from *d to *e. *n 4185459 11/07/2013 gvch added watermark as ?not recommended for new designs.? updated in new template. document history page (continued) document title: cy14c101j, cy14b101j, cy 14e101j, 1-mbit (128 k 8) serial (i 2 c) nvsram document number: 001-54050 rev. ecn no. submission date orig. of change description of change not recommended for new designs
document number: 001-54050 rev. *n revised november 7, 2013 page 31 of 31 all products and company names mentioned in this document may be the trademarks of their respective holders. cy14c101j cy14b101j cy14e101j ? cypress semiconductor corporation, 2009-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support not recommended for new designs

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